Parasitic bipolar transistors of CMOS circuits can form Silicon Controlled Rectifiers (hereinafter referred to as SCRs). An SCR typically includes two parasitic bipolar transistors that are dominantly of opposite connectivity types, such as an NPN parasitic bipolar transistor (hereinafter referred to as NPN) and a PNP parasitic bipolar transistor (hereinafter referred to as PNP). Since the NPN has two junctions of N and one junction of P it is considered to be dominantly an N-type transistor as opposed to the PNP which is considered to be dominantly a P-type transistor. To form an SCR, the collector of the NPN has to be connected to the base of the PNP, and vice versa.
When the SCR becomes activated, the process is known as latch-up. Once the SCR is in the latched state, it may continue to draw high current even if the trigger source is removed. This condition is referred to as sustained latch-up.
When sustained latch-up occurs in a CMOS circuit, the portion of the circuit affected by the latch-up becomes unusable until the power supply is cycled. Cycling the power supply removes the source of the current which sustains the latch-up. However, cycling the power supply causes down-time and needs to be done manually unless latch-up detection circuitry is being used. If the short-circuit current that flows through the SCR is large, physical damage to circuitry may also occur due to the heat generated.
CMOS circuitry is very sensitive to latch-up due to the large number of parasitic SCRs that exist in a chip and the close proximity of the NPN and PNP transistors of the SCR. The latch-up phenomenon may be explained using a simple inverter configuration in a CMOS process. FIG. 1a is a cross section of an inverter 100 including a parasitic SCR device 101. As shown in FIG. 1a, the SCR 101 includes an NPN 102 formed by Nwell 103, P-substrate 104 and N+ diffusion 105, as well as a PNP 106 formed by P+ diffusion 107, Nwell 103 and P-substrate 104. Both bipolar transistors are normally considered to be parasitic but in this context they play an essential role as latch-up forming elements. Between the base and emitter terminals of the NPN and PNP, there are two important resistors (herein referred to as “bypass” resistors): the substrate resistor RSUB and the Nwell resistor RWELL. The values of both resistors as well as the gain of both parasitic bipolar transistors determine the latch-up trigger point. FIG. 1b is a circuit schematic showing the SCR device 101 of FIG. 1a connected between VDD, VSS, and a circuit pad.
FIG. 2 is a graphical representation of a latch-up characteristic curve. The transition from high impedance to negative resistance is at the point where there is sufficient switching current (IS) and switching voltage (VS). This is the trigger point for the latch-up, which is when the SCR activates. The holding point, which occurs at the intersection of holding current (IH) and holding voltage (VH), marks the transition from negative resistance to positive low impedance. If the current and voltage drop below the holding point the SCR will turn off.
The two basic methods for preventing latch-up are: decoupling the parasitic bipolar transistors; and minimizing the bypass resistance. Reducing the bypass resistance reduces the voltage across the internal CMOS structure, thus makes the structure less likely to become latched.
To prevent latch-up from occurring, one approach is to eliminate the gain of the lateral NPN 102 and/or the vertical PNP 106. The standard method of eliminating the gain is to add proper guard rings and/or to maintain sufficient space between the NPN and PNP.
Furthermore, a parasitic SCR that is near an injector is at risk of entering latch-up. The injector is a diffusion that is capable of passing stray carriers into the substrate when voltages go out of their normal ranges. Parasitic SCRs that are not near an injector have a very low probability of entering latch-up because of the absence of a stray current that causes the necessary voltage drop that activates the SCR. Thus, another method of preventing latch-up is to physically separate the entire SCR from the injector.
FIG. 3 is top view of a typical prior art device 300 for latch-up prevention using guard rings between NPN and PNP transistors of an SCR. As shown in FIG. 3, an N+ region 301 is formed in Pwell 302, and a P+ region 303 is formed in Nwell 304. The N+ region 301 defines an NPN transistor 305 with Pwell 302, and the P+ region 303 defines a PNP transistor 306 with Nwell 304. The NPN 305 is surrounded with a P+ guard ring 307. The PNP 306 is surrounded with an N+ guard ring 308. In operation, the P+ guard ring 307 is connected to the lowest voltage rail VSS with a low impedance connection, while the N+ guard ring 308 is connected to the highest positive rail potential VDD used by the devices in the Nwell 308 with a low impedance connection. There are many subtle variations of this concept, an example of which is described in U.S. Pat. No. 6,614,078.
FIG. 4a is a cross sectional view of another prior art device 400 for latch-up prevention using space between the NPN and PNP transistors of the SCR in order to achieve additional latch-up robustness. The device 400 includes an Nwell 401, a Pwell 402, and a P-substrate 403. Nwell 401 includes two P+ diffusions 404 and 405, and an N+ diffusion 406. Pwell 402 includes two N+ diffusions 407 and 408 and a P+ diffusion 409. P+ diffusion 404 of Nwell 401 forms PNP 410 with Nwell 401 and Pwell 402. N+ diffusion 407 forms an NPN 411 with Pwell 402 and Nwell 401. PNP 410 and NPN 411 form the SCR 412. N+ diffusion 408 of Pwell 402 and P+ diffusion 405 of Nwell 401 are latch-up injectors. If the PNP 410 is activated such as through a voltage overshoot at the pad node, current in RPW3 raises the potential of Pwell 402, which could activate the NPN 411. Pwell 402 is electrically connected to P-substrate 403, and both are considered as the same terminal. However, the potential of Pwell 402 is more important than that of P-substrate 403, in that the Pwell 402 forms the junction that activates the NPN 411 when it becomes forward biased.
If the NPN 411 is activated, and draws enough current such that it can keep the PNP 410 activated, sustained latch-up occurs. An additional P+ diffusion 413 is added in Pwell 402 between P+ diffusion 409 of Pwell 402 and N+ diffusion 406 of Nwell 401, at a distance D1 of P+ diffusion 409. The distance D1 that separates P+ diffusions 409 and 413 creates a separation resistance RSEP between P+ diffusions 409 and 413. The separation between P+ diffusion 413 and Nwell 401 creates a resistance RPW1. Furthermore, a resistance RPW2 exists between P+ diffusion 413 and Pwell 402, and a similar resistance RPW3 exists between P+ diffusion 409 and Pwell 402. The configuration of these resistances is illustrated in FIG. 4b. 
FIG. 4b is a circuit schematic showing the SCR of FIG. 4a connected between VDD and VSS. The separation resistance RSEP helps the flow of additional current into RPW2, which reduces the current flowing in RPW3. Less current in RPW3 reduces the Pwell 402 potential around the NPN device, thus reducing the risk of reaching a sufficient VBE to activate the NPN.
Several of the methods discussed above require certain process options to be available. Since such options may increase the cost of fabrication or may simply not be available, these methods are not always practical. Furthermore, as the current technology aims to reduce the size of integrated circuit chips, the area consumed by guard rings and space regions affects the overall cost of producing the chip.
Therefore, it is desirable to find a new method for protecting circuits against latch-up which allows for reduced area consumption and which does not require additional process steps.